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Clause Form Conversions for Boolean Circuits
Daniel Sheridan and
Paul Jackson,
Proceedings of SAT-2004.
Copyright (c)2004
Springer-Verlag
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[pdf][ps][bib]
Short paper:[pdf][ps]
Poster:[pdf][ps]
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Bounded Verification of Past LTL
Alessandro Cimatti,
Marco Roveri and
Daniel Sheridan,
Proceedings of FMCAD-2004.
Copyright (c)2004
Springer-Verlag
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[pdf][ps][bib]
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Bounded Model Checking with SNF, Alternating Automata and Büchi Automata
Daniel Sheridan,
Second International Workshop on Bounded Model Checking
(Updated: final version to appear in ENTCS)
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[pdf][ps][bib]
Presentation:[pdf][ps]
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Dynamic Step Size Adjustment in Iterative Deepening Search
Daniel Sheridan,
Doctoral Programme at CP-2003 Copyright (c)2003
Springer-Verlag
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[pdf][ps][bib]
Extended:[pdf]
Poster:[pdf][ps]
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Symbolic Model Checking for LTL using SNF
Daniel Sheridan,
Tenth Workshop on Automated Reasoning, 2003.
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[pdf][ps][bib]
Poster:[pdf][ps]
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A Fixpoint Based Encoding for Bounded Model Checking
Alan Frisch,
Daniel Sheridan and
Toby Walsh,
Proceedings of FMCAD-2002.
Copyright (c)2002
Springer-Verlag
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[pdf][ps][bib]
Presentation:[pdf][ps]
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Fixpoint Characterisations of LTL for Bounded Model Checking
Daniel Sheridan,
Ninth Workshop on Automated Reasoning, 2002.
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[pdf][ps][bib]
Poster:[pdf][ps]
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Comparing SAT Encodings for Model Checking
Alan Frisch,
Daniel Sheridan and
Toby Walsh,
Doctoral Programme at CP-2001 Copyright (c)2001
Springer-Verlag
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[pdf][ps][bib]
Extended:[pdf]
Poster:[1][2][3][4]
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Clause Forms Generated by Bounded Model Checking
Daniel Sheridan and
Toby Walsh,
Eighth Workshop on Automated Reasoning, 2001.
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[pdf][ps][bib]
Poster:[pdf][ps]
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